IBM AT-286 Slots

62 pin slot
pin signal i/o
A2 SD7 I/O
A3 SD6 I/O
A4 SD5 I/O
A5 SD4 I/O
A6 SD3 I/O
A7 SD2 I/O
A8 SD1 I/O
A9 SD0 I/O
A12 SA19 I/O
A13 SA18 I/O
A14 SA17 I/O
A15 SA16 I/O
A16 SA15 I/O
A17 SA14 I/O
A18 SA13 I/O
A19 SA12 I/O
A20 SA11 I/O
A21 SA10 I/O
A22 SA9 I/O
A23 SA8 I/O
A24 SA7 I/O
A25 SA6 I/O
A26 SA5 I/O
A27 SA4 I/O
A28 SA3 I/O
A29 SA2 I/O
A30 SA1 I/O
A31 SA0 I/O
pin signal i/o
B1 GND -
B3 +5V -
B5 -5V -
B7 -12V -
B9 +12V -
B10 GND -
B13 -IOW I/O
B14 -IOR I/O
B15 -DACK3 O
B16 DRQ3 I
B17 -DACK1 O
B18 DRQ1 I
B19 -Refresh I/O
B21 IRQ7 I
B22 IRQ6 I
B23 IRQ5 I
B24 IRQ4 I
B25 IRQ3 I
B26 -DACK2 O
B27 T/C O
B29 +5V -
B31 GND -

18-pin slot
pin signali/o
C1 SBHE i/o
C2 LA23 i/o
C3 LA22 i/o
C4 LA21 i/o
C5 LA20 i/o
C6 LA19 i/o
C7 LA18 i/o
C8 LA17 i/o
C9 -MEMR i/o
C10 -MEMW i/o
C11 SD08 i/o
C12 SD09 i/o
C13 SD10 i/o
C14 SD11 i/o
C15 SD12 i/o
C16 SD13 i/o
C17 SD14 i/o
C18 SD15 i/o
pin signal i
D1 -MEM CS16i
D2 -I/O CS16i
D3 IRQ10 i
D4 IRQ11 i
D5 IRQ12 i
D6 IRQ15 i
D7 IRQ14 i
D8 -DACK0 o
D9 DRQ0 i
D10 -DACK5 o
D11 DRQ5 i
D12 -DACK6 o
D13 DRQ6 i
D14 -DACK7 o
D15 DRQ7 i
D16 +5 V -
D18 GND -

    The I/O channel signal description is given below. All signal lines are TTL-compatible. I/O adapters should be designed with a maximum of two low-power Shottky (LS) loads per line.

* SA0 through SA19 (I/O): These are the addres bits 0 through 19 used to addres memory and I/O devices. In addition to these addres bits, LA17 through LA23 allows acces up to 16 Mb of memory. SA0 through SA19 are gated on system bus when 'BALE' is high are latched on the falling edge of 'BALE'.

* LA17 through LA23: These signals (unlatched) are used to addres memo- ry and I/O devices within the system. They provide the system with up to 16 Mb of addressability. These signals are valid when 'BALE' is high. They are not latched during microprocessor cycle and therefore do no stay valid for the whole cycle. The purpose of these signals is to ge- nerate memory decode for 1 wait state memory cycles. These decodes should be latched by I/O.

* CLK (0): This is the 6-Mhz system clock. The clock is a synchronous microprocessor cycle time of 167 nanoseconds. The clock duty cycle is 50%. It should be used for synchronization purpose only.

* RESET DRV (O): This signal is used to reset or initialise system lo- gic at power-up time or during a low line-voltage outage. It is a acti- ve high signal.

* SD0 through SD15 (I/O): These are the data bits for the microproces- sor, memory, and I/O devices. SD0 is the least-significant bit and SD15 is the most-significant bit. All 8-bit devices on the I/O channal should use SD0 - SD7 communications to the microprocessor. For 16-bit devices, the SD0 - SD15 signals are used. To suppot 8-bit devices, the data SD8 - SD15 will be gated to SD0 - SD7 during 8-bit transfers to these devices: 16-bit microprocessor transfers to 8-bit devices will be converted to two 8-bit transfers.

* BALE (0)(buffered): The BALE (Buffered Addres Latch Enabled) is provi- ded by the 82288 Bus Controler and is used to latch valid addresses and memory decodes from the microprocessor. When used with AEN signal, it provides an indicator of valid microprocessor or DMA addres. Microproce- ssor addresses SA0 - SA19 are latched on the falling edge of 'BALE'. This signal is forsed high during DMA cycles.

* -I/O CH CK (I): the '-I/O Channel Check' provides the system with pa- rity(error) information about memory or devices on the I/O channel. When it is active (low), it indicates an uncorrectable system error.

* I/O CH RDY (I): The 'I/O Channel Ready'is used to lengthen I/O or me- mory cycle. Any slow devices should drive this signal low immediately upon detecting its valid address and a Real number of clock cycles (167 nsec.). This signal should be held low for no more than 2.5 microsec.

* IRQ3 - IRQ7, IRQ9 - IRQ12 and IRQ14, IRQ15 (I): These interrupts si- gnals are used to signal the microprocessor that an I/O needed attention. The interrupt request are prioritized, with IRQ9 through IRQ12 and IRQ14 through IRQ15 having the highest priority (IRQ9 is the highest) and IRQ3 through IRQ7 having the lowest priority (IRQ7 is the lowest). An interrupt is activated when an IRQ request line is raised from low to high. It must remained high until the microprocessor acknowledges the interrupr request (interrupt service routine).

* -IOR (I/O): The '-I/O Read' requests an I/O device to put data onto the data bus. It is an active low signal and may be driven by a micro- processor or DMA controller resident on the I/O channel.

* -IOW (I/O): The '-I/O Write' requests an I/O device to read data from the data bus. It is an active low signal and may be driven by a micro- processor or DMA controller in the system.

* -SMEMR(O), -MEMR(I/O): These signals requests the memory devices to drive data onto the data bus. '-SMEMR' is active only when the memory decode is within the low 1 Mb of memory space and '-MEMR'is active on all memory read cycles. It may be driven by any microprocessor or DMA controller in a system.'-SMEMR' is derived from '-MEMR' and the decode of the low 1Mb of memory. When a microprocessor on the I/O channel requ- ests to drive '-MEMR', the address lines must first be valid on the bus for one clock period before driving '-MEMR' active. Both signals are ac- tive low.

* -SMEMW(O), -MEMW(O): These signals request the memory device to store the data present on the data bus. '-SMEMW' is activated only when the memory decode is within the low 1Mb of memory space.'-MEMW' is activated on all memory read cycles. When a microprocessor on the I/O channel wi- shes to drive '-MEMW', the address lines must be valid on the bus for one clock period before driving '-MEMW' active. Both signals are active low.

* DRQ0-DRQ3 and DRQ5-DRQ7 (I): DMA Requests 0 through 3 and 5 through 7 are available for the peripheral devices and the I/O channel micropro- cessor to gain DMA service ( or control of the system ). These signals are prioritized ('DRQ0' has the highest priority and 'DRQ7' having the lowest). A request is generated by bringing a DRQ line to an active high state. It must be held high until the corresponding 'DMA Request Acknow- ledge'(DACK) line goes active. 'DRQ0' through 'DRQ3' perform 8-bit DMA transfers while the request lines 'DRQ5' through 'DRQ7' perform 16-bit transfers.

* -DACK0 to -DACK3 and -DACK5 to -DACK7 (O): They are used to acknow- ledge DMA requests (DRQ0 through DRQ7). They are active low signals.

* AEN (O): 'Address Enable'is provided to degate the microprocessor and the other devices from the I/O channel to allow DMA transfers to take place. When this line is active high, the DMA controller has control of the address bus, the data bus read command lines (memory and I/O), and the write command lines (memory and I/O).

* -REFRESH (I/O): This signal is used to indicate a refresh cycle and can be driven by a microprocessor on the I/O channel.

* T/C (O): 'Terminal Count' provides a pulse when theterminal count for any DMA channel is reached.

* SBHE (I/O): 'Bus High Enable' indicates a transfer of data on the up- per byte of the data bus, SD8 through SD15. It is used to condition data bus buffers tied to SD8 through SD15 for 16-bit transfer.

* -MASTER (I): This signal is used in condition with a DRQ line to gain control of the system. A processor or DMA controller on the I/O channel may issue a DRQ to a DMA channel in a cascade mode and receive a '-DACK' An I/O microprocessor upon receiving the '-DACK', may then pull '-MASTER' low. This will allow it to control the system address, data, and control lines (a condition commonly known as tri-state). After '-MASTER' is low, the I/O microprocessor must wait for one clock period before issuing a Read or Write command. This signal should held low for more than 15 mic- roseconds otherwise system memory may be lost due to lack of refresh.

* -MEM CS16 (I): 'MEM 16 Shp Select' indicates that the data transfer is a 16-bit 1-wait state, I/O cycle. It is derived from an address deco- de. It is an active low signal and should be driven with an open collec- tor or tri-state driver capable of sinking 20 mA.

* OSC (O): 'Oscillator' is a high speed clock with a 70- nanosecond period ( 14. 31818 MHz ). This signal is not synchronous with the system clock. It has a duty cycle of 50%.

* OWS (I): The 'Zero wait state' indicates to the microprocessor that it can complete the present bus cycle without inserting any additional wait cycles. In order to run a memory cycle to a 16-bit device without wait cycles, this signal (OWS) is delivered from an address decode gated with a Read or Write command. For an 8-bit device with a minimum of two wait states, 'OWS' should be driven active one system clock after the Read and Write command is active gated with the address decode for the device. Memory Read and Write commands to an 8-bit device are active on the falling edge of the system clock. 'OWS' is active low and should be driven with an open collector or tri state driver capable of sinking 20 mA.